The laminated panel is now ready for outer-layer processing. As during inner-layer processing, photoresist film is applied to each side, and the panels undergo either film or laser direct imaging. Inner layers that are typically negative images, but outer layer imaging is done with positive ones. This is because the circuit image on the photoresist is developed away, leaving the circuit copper exposed for plating.
Most PCB tools let you define unique constrained areas within a PCB. A good example is those for BGAs, where you want to have much tighter rules than apply elsewhere. DFM software should read these CAD-constrained maps. This saves the user manually reviewing all the ‘false’ DFM violations caused by using general PCB rules within those constrained areas.
One common violation on outer layers is a ‘same net sliver’ (Figure 4). While electrically correct, these present significant difficulty to the fabricator. In cases like that illustrated, the width of the photoresist (in black) is so thin it runs the risk of breaking and then redepositing elsewhere, potentially leading to a short or an open. Today’s strict and low tolerance constraints for high speed nets mean same net slivers can shorten connections and significantly change circuit impedance.
Final PCB processing begins with the application of solder mask and silkscreen. Typical solder mask checks include rules that govern how closely lines can pass to a pad and how close two pads can be.
Lines that pass closely must be fully covered by mask to avoid solder bridging between the line and pad. If we again consider process tolerances, the application of photo-imageable solder mask has a positional tolerance of +/- 3 mils or .08 mm. It is important that you have at least this much clearance around your solder mask pads.
DFM can also identify very small slivers of solder mask between two pads. If a piece of mask detaches, the cause is typically a bad solder joint that has resulted in mask debris becoming embedded in the solder. This can cause a bad connection or even an open depending on the size of the mask fragment compared to the size of the joint. Below a minimum web width of around 0.1 mm, the fabricator must use a gang solder mask.
These issues may not be identified at the design stage because many PCB designers follow IPC’s recommendation to create solder mask 1:1 with the pad. The idea is that the fabricator will add the necessary growth to the mask for its process. However, by ignoring this at the design stage, you run the risk that these solder mask issues, once found by your fabricator, will cause a delay while you change the layout or approve the use of a gang mask.
Silkscreen can cause other problems. It should never be applied on pads because it is considered a solder contaminant and will prevent the formation of a quality joint. If the defined silkscreen uses a stroke size too small for the screen printer to image, it is probably too small to serve its purpose. The fabricator will consequently seek permission to increase the line width or to remove it from the legend. Although this may not be a fatal error, it is another possible source of delay.
One last step remains before test. The fabricator separates the panels into individual PCBs and makes all internal cutouts or routs. Here the design must maintain a minimum copper setback from board or slot edges to avoid damaging the circuits. Keep in mind that most CNC routing is going to have a mechanical tolerance of +/- 10 mils or .25 mm.
Without good DFM verification practices during design, many of these issues will arise as the board now goes to electrical test, carried out with a flying probe or flying grid tester for low volumes or with a bed-of-nails tester for higher volumes.
The more aware you are of your fabricator’s perspective, the fewer issues you will have once you release your PCB design to manufacturing. Do not to wait until your fabricator discovers these problems but use DFM verification software during the design process so that your fabricator will be just as happy with your design as you and your layout tool.